Television receivers necessarily include a number of adjustable controls for establishing desired operation and optimizing picture quality. Examples of these are the brightness, contrast, and color controls.
Viewer operated controls, in addition to being a source of inconvenience, are also subject to gross mis-adjustment, occasionally requiring a service call to re-establish proper operation. To alleviate such problems, it is desirable to incorporate into the design of television receivers automatic control circuits tending to obviate the need for, or at least abate the use of, viewer-operated controls.
U.S. Pat. No. 3,920,891 granted to D. W. Rhee discloses a novel Peak Detector and Sample and Hold Circuit for use with amplitude control circuits. Rhee discloses circuits effecting both positive and negative peak detectors, thereby establishing a method for controlling the amplitudes of signals of either polarity. Rhee's circuit also circumvents the disadvantages attendant a long time-constant in the detector filter circuit. In particular, Rhee employs a sampling circuit to monitor the operation of a peak detector. If the peak detector is not driven into conduction at least once during approximately three vertical fields, an indication that it has not followed a change in input signal level, the detector filter network is discharged. This allows the detector to re-charge the output filter network to a level approximately equal to the peak amplitude of the input signal.
The Peak Detector and Sample and Hold Circuit disclosed in Rhee can be implemented almost entirely with integrated circuit techniques. However, the sampling circuit which monitors the operation of the peak detector requires a relatively large value capacitance, not readily realizable in integrated circuit form. Therefore, each Peak Detector and Sample and Hold Circuit included in an integrated circuit package requires two individual external capacitors, one in the detector filter circuit and one to establish the sampling time delay.
Because there is a limit to the number of pins that can be provided on an integrated circuit package at a given price and because the capacitor itself is a relatively expensive component, it is desirable to minimize the number of external capacitors required. The circuitry of this invention allows a plurality of peak detectors to be monitored with a single time delay capacitor.